VLSI Laboratory is one of the very important lab of the ECE department, in which the M.Tech. students of VLSI stream perform Analog and digital VLSI IC design experiment using cadence Virtuoso simulator tools in 180 nm CMOS process. During the even semester the PG student perform Digital Logic Design using Verilog and VHDL simulator software. They also perform lab using Matlab software tool in the even semester. In this lab the PG and Ph.D. students perform their project and Ph.D. research work.